Small FPGA project. FPGA

FPGA (Programmable Logic Integrated Circuit) is an integrated circuit designed to build digital circuits from a description in a special programming language. In other words, an FPGA is a chip, as it were, containing a bunch of elements like the 74HCxx. What kind of logical elements these will be, what connections will be between them, and what connections the resulting circuit will have with the outside world, is determined at the FPGA programming stage.

Note: As far as I could find out, in Russian today the terms FPGA and FPGA (Field-Programmable Gate Array, User-Programmable Gate Array) are considered interchangeable, which will be used further in the text. However, it is worth knowing about the existence and an alternative point of view, according to which FPGA (FPGA) is one of the varieties of FPGA (PLD, Programmable Logic Device).

FPGA Basics

For FPGA programming, hardware description languages ​​(HDL, Hardware Description Language) are used. Among them, the most popular are Verilog (and its dialects, in particular SystemVerilog), as well as VHDL. The languages ​​are similar in many ways, but have different syntaxes and differ in some details. If Verilog is such a C of the hardware description world, then VHDL is, respectively, Pascal. As far as I know, VHDL is somewhat less popular, in part due to its verbosity compared to Verilog. Of the advantages of VHDL (or disadvantages, as anyone) can be called strict static typing. Verilog sometimes allows implicit casting. Continuing the analogy with C and Pascal, the languages ​​don't differ so much that you can't learn both of them.

Currently, the leading FPGA manufacturers are Altera (now owned by Intel) and Xilinx. According to information from various sources, together they control at least 80% of the market. Other players worth noting are Actel (acquired by Microsemi), Lattice Semiconductor, Quicklogic and SiliconBlue. You can work with Xilinx hardware only from the Xilinx development environment (called Vivado), and the Altra development environment (called Quartus) understands only Altera hardware. That is, a full vendor lock, and choosing a specific FPGA for your project, you automatically select the development tools of the corresponding manufacturer, their technical support, documentation, software licensing conditions, the policy regarding the termination of hardware support, and so on.

FPGAs are often used in tasks where you want to speed up some calculations by implementing them right in the hardware. For example, FPGAs are widely used in signal processing, such as oscilloscopes, spectrum analyzers, logic analyzers, signal generators, Software Defined Radio, and even some monitors. In particular, the LimeSDR uses the Altera Cyclone IV, and the Rigol DS1054Z oscilloscope uses the Xilinx Spartan-6, as well as the ProASIC 3 from Actel. Other applications I've heard of include computer vision, speech recognition, and bioinformatics. There are other projects, in particular for the development of web servers and DBMS running on FPGA. But as far as I know, this direction is still highly experimental.

Xilinx or Altera?

That being said, the best Linux is the one that your fellow Linux guru uses.

My friend, an FPGA guru, Dmitry Oleksyuk, advised me to start with the Arty Artix-7 devboard from Digilent. The FPGA used in it is Artix-7 from Xilinx. Digilent itself does not ship to Russia, but the device is also available on AliExpress, albeit with a noticeable markup (the official price is $ 99). It is also sold on eBay. This is a pretty powerful board, which nevertheless costs adequate money.

Fun fact! If you just want to program in Verilog or VHDL, strictly speaking, you don't need to buy any FPGA board. At first, you can limit yourself to a simulator, the work with which will be discussed later.

An interesting feature of the board is the arrangement of the slots in a way compatible with Arduino shields. Also included with the board is an insert for obtaining a license for Vivado, which opens up all its possibilities. The license is valid for one year from the date of activation, and is also tied to one computer by OS type and MAC address.

On delivery. I have heard that devices with FPGAs on board have a good chance of not clearing customs. The store on AliExpress, the link to which I gave above, delivers boards to Russia through the SPSR courier service. To go through customs, it was required to fill out an online form with passport data (only data, no photo) and a contact phone number, as required by current Russian legislation. After that, the board was delivered by courier right to the door without any questions.

Installing Vivado

The Vivado development environment is available for download on the Xilinx website. Be mentally prepared for the fact that before downloading you will have to register and fill out a fairly detailed form about yourself. Download the archive called "Vivado HLx 2017.2: All OS installer Single-File Download". Do not accidentally confuse it with any "Vivado Lab Solutions", this is absolutely not what you need. The archive weighs over 20 GB, so we need to be patient.

Unpack the archive, run the installer. Install Vivado HL System Edition. Its full version will take up 47 GB of disk space. Personally, I unchecked the Software Development Kit and left support for only 7 Series devices, which reduced the size to 12 GB. Running a little ahead, I will note that this configuration turned out to be quite enough.

Before launching Vivado, you need to add support for Arty Artix-7 to it, since it doesn't know anything about this board out of the box. It is done somehow like this:

cd ~ / opt / xilinx / Vivado / 2017.2 / data / boards / board_files
wget https: // github.com/ Digilent / vivado-boards / archive / master.zip
unzip master.zip
mv vivado-boards-master / new / board_files / * ./
rm -r vivado-boards-master
rm master.zip

Also download and save the Arty_Master.xdc file somewhere. We will need it further. The file contains a description of the LEDs on the board, switches, and so on. Without it, blinking the LEDs on the Verilog won't be easy.

First project on SystemVerilog

In Vivado, say File → New Project ... Select RTL Project as the project type, check the Do not specify sources at this time checkbox. In the board type selection dialog, find Arty in the list.

First of all, add the previously downloaded XDC file to the project. Copy it to the project directory. Then we say File → Add Sources… → Add or create constraints → Add Files, find a copy of the file, click Finish. The file Arty_Master.xdc, or whatever you named the copy, will appear in the project files tree (Sources) in the Constraints group. Open it up and uncomment all the lines in the Clock signal, Switches and LEDs groups.

Then we say File → Add Sources… → Add or create design sources → Create File. In the file type, select SystemVerilog, in the file name, enter something like hello. We say Finish. Next, the Define Module dialog will appear, which will offer you to click on the module interface. The dialog is pretty useless, because it's more convenient to do the same right in the code, so click Cancel.

Find a new file hello.sv in the source tree, it will be in the Design Sources group. Open up and write the following code:

`timescale 1ns / 1ps

module hello (
input logic CLK100MHZ,
input logic [3: 0] sw,
output logic [3: 0] led
) ;

always @ (posedge CLK100MHZ)
begin
if (sw [0] == 0)
begin
led<= 4"b0001 ;
end
else
begin
led<= 4"b0000 ;
end
end

endmodule

If everything was done correctly, at this stage your Vivado will look something like this (clickable, PNG, 71 KB):

Compilation of a program is carried out in two stages - synthesis and implementation. At the synthesis stage, the program is translated into an abstract circuit of logic gates and other elements. At the stage of implementation, a decision is made on how to flash this circuit into a specific piece of hardware.

Let's run the synthesis by saying Flow → Run Synthesis, or simply by pressing F11. In the upper right corner, you will see an indication that the process is in progress. It can take quite a long time, depending on your computer and the complexity of the program. On my laptop, the synthesis of the above program was completed in about 10 seconds. If now we say Flow → Open Synthesized Design, then you can see a beautiful picture like this:

It's time to flash our board. We say Flow → Run Imlementation, then Flow → Generate Bitstream. We connect the board to the computer via USB, in Vivado we say Flow → Open Hardware Manager → Open target → Auto Connect → Program device. You will need to specify the path to the bit-file. I had it as follows:

./first-project.runs/impl_1/hello.bit

We say Program. The LD4 LED on the board is now on if the SW0 switch is down (see the photo of the board above). If the switch is up, the LED is off. Simple, of course, but this is "hello, world", what did you expect? :)

Simulation

Simulation is a virtual execution of code in Verilog or VHDL right on your computer, without any FPGAs. It is both a debugging tool and a kind of framework for covering code with tests.

When I got to know the simulation, the first thing I discovered was that it didn't work for me. The logs were simple:

ERROR: Failed to compile generated C file [...] xsim_1.c.

Google on this error found only all sorts of nonsense in the style of "try to disable your antivirus." In the end, adding the -v 2 flag to the ~ / opt / xilinx / Vivado / 2017.2 / bin / xelab script helped to solve the problem. With its help, I found out that Clang, the binary of which Vivado drags along, crashes with the following error:

/ a / long / path / to / clang: error while loading shared libraries:
libncurses.so.5: cannot open shared object file: No such file or
directory

And this error and its solution are already described on the Arch Wiki. Personally, I just copied an already existing file from the Vivado_HLS directory:

cp ~ / opt / xilinx / Vivado_HLS / 2017.2 / lnx64 / tools / gdb_v7_2 / libncurses.so.5 \
~ / opt / xilinx / Vivado / 2017.2 / lib / lnx64.o / libncurses.so.5

... after which everything worked. So, now, actually, an example of a simulation.

Similar to how we created hello.sv earlier, create a new file hello_sim.sv in the Simulation Sources group. We write the following code in the file:

`timescale 1ns / 1ps

module hello_sim ();
logic clck_t;
logic [3: 0] sw_t;
logic [3: 0] led_t;

Hello hello_t (clck_t, sw_t, led_t);

initial begin
clck_t<= 0 ;
sw_t<= 4"b0000 ; # 1 ; clck_t <= 1 ; # 1 ; clck_t <= 0 ; # 1 ;
assert (led_t === 4 "b0001);

Sw_t<= 4"b0001 ; # 1 ; clck_t <= 1 ; # 1 ; clck_t <= 0 ; # 1 ;
assert (led_t === 4 "b0000);
end

endmodule

In the source tree, right-click on the file, select Source Node Properties. In the Used In section, uncheck the Synthesis and Implementation boxes. We don't want any tests to clog up our far from rubber FPGA, do we?

Now we say Flow → Run Simulation → Run Behavioral Simulation. As a result, you will see something like this:

You can see that when sw is zero, led is one, and vice versa. In this case, all changes occur on the edge of the clock signal. The program appears to be working correctly. Well, nothing fell on the asserts, which seems to be hinting.

Conclusion

The archive with the project described above can be downloaded. I would recommend the following as additional sources of information:

• If you are interested in hardware details, pay attention to

Imagine that the processor, instead of executing a set of instructions, will rebuild for each program and turn the algorithm directly into hardware. This is how FPGAs work! In this article, I will explain how this is possible and introduce you to different ways of FPGA design.

Maybe you know how to hack devices on the other side of the world or code awesome web applications, but do you understand how your computer works? And it's not about what the operating system does, how the garbage collector functions in Java, or how the C ++ compiler works. I'm talking about the lowest, hardware level, below assembler: how the hardware works.

What happens to the NIC chip when an Ethernet packet arrives? How is this packet passed on to the computer's RAM via the PCI Express bus? How do the fastest hardware image recognition systems work?

To answer these questions, you need to understand a little about the digital logic of ASICs, but starting with them is very difficult and expensive, and it is better to start with FPGAs instead.

INFO

FPGA stands for field-programmable gate array, in Russian - programmable gate matrices, FPGA. More generally, they are called FPGAs - programmable logic integrated circuits.

With FPGAs, you can literally design digital microcircuits while sitting at home with an available debug board on your desk and developer software for a couple of kilo-bucks. However, there are free options as well. Note: exactly to design, not to program, because the output is a physical digital circuit that performs a certain algorithm at the hardware level, and not a program for the processor.

It works like this. There is a ready-made PCB with a set of interfaces that are connected to an FPGA chip installed on the board, like a cool board for a data center or a debug board for training.

Until we configure the FPGA, there is simply no logic inside the microcircuit to process data from the interfaces, and therefore nothing will obviously work. But as a result of the design, a firmware will be created, which, after loading into the FPGA, will create the digital circuit we need. For example, you can create a 100G Ethernet controller that will receive and process network packets.

An important feature of FPGAs is the ability to reconfigure. Today we need a 100G Ethernet controller, and tomorrow the same board can be used to implement independent four 25G Ethernet interfaces.

There are two major FPGA chip makers, Xilinx and Intel, which control 58% and 42% of the market, respectively. The Xilinx founders invented the first FPGA chip back in 1985. Intel recently entered the market in 2015 by acquiring Altera, which was founded at the same time as Xilinx. Xilinx and Altera technologies are similar in many ways, as are development environments. Most of the time I have worked with Xilinx products, so don't be surprised at the constant mention of it.

IMPLEMENTATION OF THE PROJECT ON FPGA

After working out the logic circuit using functional modeling, it is necessary to place it on the chip. Then simulate the circuit based on the actual latency of the elements obtained after placing the circuit on a chip. If necessary, correct the received solutions. After that, the circuit is loaded into the FPGA and tested at the stand.

Rice. 82. Stages of designing a digital device on FPGA

The main stages of design on FPGA (from lectures):

The device diagram is developed and entered into XILINX.

Executed by IMPLEMENTATION (translation, schema formation by extracting library elements, optimization, on-chip placement).

Programming.

1. Associative memory. Organization, sampling method, differences from address memory.

Associative access implements a search for information by some attribute, and not by its location in memory (address or place in the queue). In the most complete version, all words stored in memory are simultaneously checked for compliance with a feature, for example, for the coincidence of certain word fields (tags - from the English word tag) with the feature specified by the input word (tag address). The output is given the words that satisfy the criterion. The discipline of issuing words, if several words satisfy the tag, as well as the discipline of writing new data, may be different. The main area of ​​application of associative memory in modern computers is data caching.

In associative storage devices, information is searched for by an associative feature recorded in each memory cell.

A word is written in the mask register that allows a query for all or only some bits of the associative attribute; the use of a mask allows you to reduce or expand the search area.

Information search is performed in parallel across all cells by comparing the request with the associative attribute of each cell.

The search result is formed by a special combinational circuit that generates signals that notify about the absence of words that meet the search conditions, about the presence of only one word, about the presence of several words with such an associative feature.

After the formation and processing of the warning signals, the control circuit reads the necessary information. When writing, a free cell is searched for by the value of the busy bit, information is written into the first found free cell.

Checking the busy bit is performed by setting the n-th bit (busy bit) of the mask. When using additional combinational circuits in the associative memory, you can perform various logical operations, determining the maximum or minimum number, the number of words having the same associative attribute, etc. The memory cells of the associative memory must be static memory elements; in the associative memory, all cells are accessed simultaneously and must not be interrupted by regeneration cycles. Associative memory is the fastest, but very expensive, since it requires the introduction of an additional comparison scheme that allows you to perform a search for each memory cell. Therefore, such memory is usually not used in its pure form, and high-speed memory devices such as Cache are usually executed as partially associative.

Vfully associative cache memory (FACM, Fully Associated Cache Memory), each cell stores data, and in the "tag" field - the full physical address of the information, a copy of which is recorded. In any exchange, the physical address of the requested information is compared with the "tag" fields of all cells, and if they match, the Hit signal is set in any cell.

When reading and the value of the Hit = 1 signal, the data is sent to the data bus, if there are no matches (Hit = 0), then when reading from the main memory, the data along with the address is placed into a free or most recently unused cache memory cell.

When writing data, together with the address, first, as a rule, are placed in the cache memory (in the detected cell at Hit = 1 and free at Hit = 0). Copying data to main memory is performed under the control of a special controller when there are no memory accesses.

FACM memory is a very complex device and is used only for small capacities, mainly in special applications. At the same time, this type of cache memory provides the greatest functional flexibility and conflict-free addresses, since any unit of information can be loaded into any cell of the cache memory.

From lectures:

Associative storage devices

The fundamental difference is that the system for retrieving information from them is not carried out at a unique address where the information is located, but by some attribute, which is, in fact, part of the required information.

Information

A tag is a distinguishing feature, by coincidence with which a piece of information gets.

Simplified diagram of the associative memory:

The storage area is an addressable memory with numbered cells that stores information and tags.

To access associative memory, a sample of the required tag is placed on the request register. The comparison scheme compares the query. Set a match on the match register where the tag from memory matched the pattern. Reactions are possible (no matches; there is at least one match - in this case, the found cell is placed in the data register; multiple match - the CC must decide which of the cells to get for processing).

Application: DB, knowledge base, PC as a cache.

65 nanometers is the next target of the Zelenograd plant "Angstrem-T", which will cost 300-350 million euros. The enterprise has already submitted an application for a soft loan for the modernization of production technologies to Vnesheconombank (VEB), Vedomosti reported this week with reference to Leonid Reiman, chairman of the board of directors of the plant. Now "Angstrem-T" is preparing to launch a production line for microcircuits with a 90nm topology. Payments on the previous VEB loan, for which it was purchased, will begin in mid-2017.

Beijing collapses Wall Street

Key US indices marked the first days of the New Year with a record drop, billionaire George Soros has already warned that the world is expecting a repeat of the 2008 crisis.

The first Russian consumer processor Baikal-T1 at the price of $ 60 is launched into mass production

The company "Baikal Electronics" in early 2016 promises to launch into industrial production the Russian processor Baikal-T1 worth about $ 60. Devices will be in demand if this demand is created by the state, market participants say.

MTS and Ericsson will jointly develop and implement 5G in Russia

Mobile TeleSystems PJSC and Ericsson signed an agreement on cooperation in the development and implementation of 5G technology in Russia. In pilot projects, including during the 2018 World Cup, MTS intends to test the developments of the Swedish vendor. At the beginning of next year, the operator will begin a dialogue with the Ministry of Telecom and Mass Communications on the formation of technical requirements for the fifth generation of mobile communications.

Sergey Chemezov: Rostec is already one of the ten largest machine-building corporations in the world

In an interview with RBC, the head of Rostec, Sergey Chemezov, answered sharp questions: about the Platon system, the problems and prospects of AVTOVAZ, the interests of the State Corporation in the pharmaceutical business, spoke about international cooperation in the face of sanctions pressure, import substitution, reorganization, development strategies and new opportunities in difficult times.

Rostec "fenced off" and encroaches on the laurels of Samsung and General Electric

The Rostec Supervisory Board approved the "Development Strategy until 2025". The main objectives are to increase the share of high-tech civilian products and catch up with General Electric and Samsung in terms of key financial indicators.

The article makes an attempt to determine the composition of the accompanying documentation for the developed digital modules for programmable logic integrated circuits (FPGA). This accompanying documentation must be provided by the developers to the consumer / customer for the successful further use of the developed digital module in their projects at the design stage of digital devices based on FPGAs.

Introduction

So, what kind of design documentation should be asked from the developer, if the firm or customer enterprise or another developer will use a “foreign” developed device in their projects in the future? This article can serve as a "cheat sheet" in order to first correctly issue a technical assignment for the development of a digital device for an FPGA, and then ask the developer for design documentation for an already developed digital device. Based on previous experience with design documentation, usually an enterprise or firm uses the following standards and regulations:

• GOST 2.102-68 ESKD. Types and completeness of design documents.
• GOST 15.101-98. System of product development and launching into production. The procedure for performing research work.
• GOST R 15.201-20-00. System of product development and launching into production. Products for industrial and technical purposes. The procedure for the development and launch of products for production.

As a rule, these were a firmware file and a program (a description of a digital device in VHDL / Verilog or a set of digital circuits developed in a circuit editor using library elements of digital logic, such as triggers, registers, counters, decoders, etc.) on CD or DVD and programming instructions. And that's all.

The author, for example, ran into the following problem. One of the employees developed a sophisticated multi-module digital device. He described all the modules in VHDL, and looked at the operation sequences of these modules and the digital device as a whole on a good and expensive oscilloscope. He did not know about Test Bench files and about the possibility of modeling or did not know how to write them, by the way, there were no comments on the project and on the descriptions of the modules either. The situation can be even worse if the modules are represented by digital circuits developed in a schematic editor using library elements. This is one of the main drawbacks: apart from the developer himself, hardly anyone else will understand this digital device, especially if the project is multi-module, and the description of each module is more than 100 lines or more than one monitor screen. So, if another developer wants to introduce such an already developed digital device for FPGAs into a new development or project, he again needs to spend time developing this digital device.

The history of the design for FPGAs

Currently, the FPGA market is one of the most dynamically developing ones. FPGAs are used in many branches of technology. At the moment, there is no unambiguous methodology for obtaining the FPGA configuration from the functional model of the device at the system level that satisfies all hardware developers. The most popular approach to solving this problem is the use of IP-core technology (Intellectual Property Cores). IP cores are ready-made components that allow you to easily integrate them into your own project to create a more complex system. This approach has one significant drawback - the attachment of IP nuclei to the elemental basis. Each IP-core is optimized for a specific series of microcircuits of a particular manufacturer, which significantly impairs the ability to transfer already created devices from one element base to another. The closed nature of commercial CAD architectures makes it impossible to add your own functional device models at the system level to obtain device models based on them at the register transfer level (RTL). The development of a digital module is carried out in the form of a digital circuit drawn in a circuit editor using the library of basic circuit elements built into the manufacturer's CAD system, such as triggers, decoders, counters, adders, etc.

Another popular approach that allows for the transition from a functional model at the system level to a device model at the register transfer level is the use of hardware description languages ​​at the system level (system-level design languages, SLDLs). Such languages ​​include SystemC, Handel-C, VHDL, Verilog, System Verilog. The main advantage is independence from the hardware basis in which the device will be implemented.

Thus, on the one hand, when using the technology of IP-cores, the hardware developer receives a high-quality solution, but rigidly tied to the hardware basis in which the device is implemented. On the other hand, when using hardware description languages ​​at the system level, the device implementation is hardware independent. It follows from the above that at present, it is relevant to jointly use digital modules in the hardware description language and IP cores of the manufacturer (Xilinx, Altera, Actel, etc.) and third-party developers to accelerate the design process. When using third-party digital modules, sometimes there is a lack of information content of the accompanying documentation.

Providing information about the developed digital module for FPGA

Depending on the methodology for obtaining the FPGA configuration according to the functional model of the device at the system level, the developer can distinguish the following types of digital module for FPGAs:

• Software - a developed digital module transmitted to the consumer in the form of a description in the hardware description language (VHDL, Verilog) or / and developed in the Schematic Editor for further use in programs for automated synthesis of logic circuits and optimized in terms of functional parameters.
• Firmware - a digital module developed by a third-party developer, which is called the IP-core, transferred to the consumer in the form of a logic circuit (netlist) in the basis of the logic element library of the FPGA manufacturer and optimized for functional and electrical parameters.

At the stage of developing documentation, based on personal experience, it is necessary to draw up, in addition to the usual design documentation and technical specifications, performed in accordance with GOST 15.101, GOST 15.201, GOST 2.102, GOST 2.114, documentation for all types of models (system, logical, schematic) created at the design stages of digital devices on FPGA.

In other words, the set of design documentation for a digital device for FPGAs, in addition to the firmware file, programming instructions and the recorded project on CD / DVD, should also include accompanying documentation.

Table. List of sections of accompanying documentation

Section title	View
	Software	Firmware
General information
Purpose and scope	O	R
Specifications	O	O
Description of reset signals	O	O
Description of sync signals	O	O
Description of interfaces	O	R
Timing charts	R	O
Description of control registers	O	O
Structural (functional) diagram	R	R
Programming guide	O	O
FPGA model or family, company manufacturer	R	O
Presentation of the digital module for logic design on FPGA
RTL model	O	No
Logical model	No	O
Design constraints	O	O

Here is a list of sections (table) that should be included in the accompanying documentation for the project of a digital module for FPGAs. For each section, signs of the need to include a section in the set of documents are shown:

• "О" - a mandatory supplied section;
• "R" - section recommended for delivery.

Recommended file formats for transferring accompanying documentation - MS Word, PDF (best format), HTML. Description files in the hardware description language (VHDL, Verilog) or / and developed in the Schematic Editor are provided as required by the CAD software for development. An exception may be the additional provision in a graphic format (JPEG, BMP) of digital schematic files developed in the Schematic Editor.

General information

This section describes general information about the developed digital module in the form of a description:

• functional diagram and its constituent blocks / parts;
• reset signals, synchronization;
• used interfaces;
• control registers;
• timing chart;
• programming.

Purpose and scope

The purpose of the digital module and its scope are determined.

Specifications

A description of its main technical characteristics is given, such as performance, power consumption for a specific FPGA crystal, the number of occupied gates, and the type of FPGA crystal used. Additionally, the FPGA manufacturer used in the development of the digital CAD module and the software used for modeling and verification are indicated. For all programs used, the version and installed updates are indicated. A graphical representation of the digital module in the form of a "black box" with the designation of external inputs / outputs is given and a brief description of their purpose is given.

Description of reset signals

Details of the reset signals are given:

• List of external and internal reset signals.
• Timing parameters and timing diagrams of reset signals.
• Circuits for generating internal reset signals, if any, are included in the digital module.
• Relationship with other signals (especially with synchronization signals).

Description of sync signals

Details of the sync signals are given:

• description of external synchronization signals;
• timing parameters of synchronization signals;
• description of internal synchronization signals and their generation schemes;
• timing relationships between synchronization signals from different sources;

Description of interfaces

Features of the use of all interfaces that are part of the developed digital module, preferably unified for organizing interaction with other nodes of the system on a chip, are given. Additionally, an Internet link to a complete description of the standard interface is provided, or the description of the interface itself is provided. At the moment, interfaces to the bus AMBA, PLB, Wishbone are accepted as unified interfaces for digital modules.

Timing charts

The necessary information for organizing data exchange through the interfaces and other inputs / outputs of the digital module is provided: a graphical presentation of timing diagrams, a description of data transfer protocols, requirements for external signals supplied to the digital module (duration, frequency, etc.), and other information ...

Description of control registers

A description of all control registers of the digital module is provided. A typical description of a control register contains the name of the register, the address of the register in the internal address space, the initial value after removing the reset signal, the type of access (read / write), and a description of the internal fields.

Structural (functional) diagram

An image of the internal structure of the connections of the main internal nodes / blocks of the digital module is shown, as well as their short text description. Additionally, a description of the main internal blocks of the digital module is given. The purpose of this document is to provide the consumer with the information necessary to understand the principles of the digital module.

The number of described blocks and the scope of the description are determined by the developer of the digital module. Preferably, the minimum number of the described modules corresponds to the number of elements of the structural (functional) circuit of the digital module.

A typical description of the indoor unit contains:

• the purpose of the block;
• structural (functional) block diagram (if necessary);
• modes and algorithms of work;
• timing diagrams of work;
• block management organization;
• organization of communication with other blocks;
• any other information.

Programming guide

Provides all the necessary information about the process of programming using the CAD manufacturer of the digital module in the FPGA, the required tools for software development and debugging, software libraries.

FPGA model or family, manufacturer

For the Firmware of a digital module, the manufacturer of the FPGA, the model or family of FPGAs and its speed characteristics are indicated. For the Software digital module, information is provided on the amount of resources occupied, the requirements for the applied FPGA.

Representation of a digital module for logical design

The article discussed the difficulties in using a "foreign" project in VHDL - the lack of suitable guidelines for naming and rules for writing programs. It also provided general guidelines for naming, good form rules for writing programs, and guidelines for synthesizing. These questions should be discussed with the developer in as much detail as possible if in the future you plan to continue development or modernization on your own, before he starts developing the RTL model of the digital module on the FPGA. This especially applies to the type of software digital module on the FPGA. The same part of the article describes the general requirements for the entire project of the developed digital module on the FPGA. Here are the issues that you should pay attention to when drawing up a technical assignment for the development of a digital module on an FPGA, and especially this concerns the transfer of work results.

RTL model

A digital module described in a synthesized subset of the Verilog language or VHDL or / and developed in the Schematic Editor is intended for use at the stage of logical FPGA synthesis. Delivered to Software as an assembled project of a digital module in CAD from an FPGA manufacturer. For digital Firmware, the RTL model is provided by separate agreement.

In addition to the RTL model files, the following are transferred:

• Instructions for using the model.
• Description of the memory blocks included in the model, including the memory type, size, number of memory blocks, hierarchical name of the memory block.
• Description of the process of creating ready-made kernels using programs for their creation (for example, CoreGenerator for Xilinx ISE). In the absence of descriptions, there may be limitations for redesign and application due to technology and manufacturer dependencies.
• In the case of using a microprocessor from the manufacturer (for example, from Altera - Nios processor; from Xilinx - Microblaze, PowerPC microprocessors), a description of the process of configuring the processor core and its peripherals is required.
• A set of tests (Test Bench files) for verification and simulation of a digital module, written in the Verilog language or / and in VHDL, or / and in System Verilog.
• Any other additional information.

Logical model

The model is a list of nets, described using Verilog or VHDL in the FPGA manufacturer's library basis, and supplied for the Firmware of the digital module.

In addition to the files of the logical model, the following are transferred:

• Instructions for using this model.
• A set of tests (Test Bench files) for verification and simulation of a digital module, written in the Verilog language or / and in VHDL, or / and in System Verilog.
• Guidelines for working with a set of tests for modeling and verification of a digital module.
• Any other additional information.

Design constraints

Design constraints are provided in the form of a file describing a set of constraints imposed on a digital module when it is included in the logical system-on-chip model. This set includes clock constrains, timing constrains, constraints on how a digital module interacts with other modules, and the operating conditions for a digital module. The preferred format is Synopsis Design Constraints (SDC) or FPGA manufacturer's CAD format.

An example list of limitations for synchronization signals:

• time diagram (Clock waveform);
• clock frequency instability (Jitter);
• changing the phase of the clock frequency;
• duration of switching times (Transition times);
• Generated clock waveforms
• any other additional information.

A set of limitations for timing signals is mandatory for Software and Firmware digital modules.

An approximate list of time restrictions:

• Arrival times at inputs;
• time of appearance of signals at outputs (Required times at outputs);
• multi-cycle paths;
• false paths;
• the duration of the data signal transition times;
• any other additional information.

Conclusion

The given composition of the accompanying documentation for the developed digital modules for FPGAs is provided by agreement between the consumer and the developer. Most often, the developer provides a simple digital module, described in VHDL, Verilog, System Verilog and / or developed in a schematic editor. Regarding additional documentation, the answer from the developer is most often the following: “The digital module works, so take it and use it. There is nothing complicated in describing a circuit in the language of hardware: you will figure it out for yourself. "

In the author's opinion, you can figure out anything, it all depends on the desire and the time spent, and the time spent trying to figure out a “foreign” project for an already developed digital module is directly proportional to the experience of describing hardware in VHDL, Verilog and knowledge digital and microprocessor circuitry. This can be avoided if you initially agree with the developer on the composition of the accompanying documentation, then the use of the digital module in your project becomes easier, and its implementation will take place faster.

Summing up, the author would like to note that when formulating the task of developing a digital device on an FPGA, one should adhere to the recommendations given in the article, then there will be no problems when reusing or upgrading a previously developed digital device.

Literature

1. Denisov A. Several tips for designing digital devices on VHDL for FPGAs // Components and technologies. 2009. No. 12.
2. GOST 2.102-68 ESKD. Types and completeness of design documents.
3. GOST 2.114-95 ESKD. Technical conditions.
4. GOST 15.101-98. System of product development and launching into production. The order of performing scientific research work.
5. GOST R 15.201-20-00. System of product development and launching into production. Products for industrial and technical purposes. The procedure for the development and launch of products for production.